The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0
By Andrew Waterman, Yunsup Lee, David A. Patterson, K. Asanovi. 2014
442 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/097d9b196e215e2b65fabf8c94271d4075571c55
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Luca Benini
- Victor Costan
- Marcus Peinado
- Srini Devadas
- Ilia A. Lebedev
- Taesoo Kim
- Hyesoon Kim
- Srinivasan Murali
In Hardware and Architecture
- Taesoo Kim
- Ming-Wei Shih
- Sangho Lee
- Victor Costan
- Srini Devadas
- Luca Benini
- Marcus Peinado
- Ilia A. Lebedev
Citations in the corpus
- Sanctum: Minimal Hardware Extensions for Strong Software Isolation (2016, methodology): “Our prototype targets the Rocket Chip [32], an open-sourced implementation of the RISC-V [51] [53] instruction set architecture, which is an open standard.”
- The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology (2019, background): “Abstract—The open-source RISC-V ISA [1] is gaining traction, both in industry and academia.”
- Inferring Fine-grained Control Flow Inside SGX Enclaves with Branch Shadowing (2016, methodology): “Further, Sanctum aims to bring minimal modifications to the RISC-V Rocket Core, which also supports static and dynamic branch prediction.”