Hybrid transactional memory

By P. Damron, Alexandra Fedorova, Yossi Lev, Victor Luchangco, Mark Moir, Daniel Nussbaum. ASPLOS XII, 2006

508 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

NOrec: streamlining STM by abolishing ownership records (2010, methodology): “In HyTM, for example [6], read and write barriers are inserted in hardware transactions in order to inspect orecs.”
Transactional Memory, 2nd edition (2010, methodology): “• The Sun C++ compiler with Transactional Memory supports a range of STM back-ends, including TL2 [83], SkySTM [188], HyTM [78] and PhTM [193].”
Transactional boosting: a methodology for highly-concurrent transactional objects (2008, methodology): “This approach has been investigated in hardware [14, 21], in software [8, 9, 13, 27], and in schemes that mix hardware and software [ 6 , 25].”
Transactional memory (2010, methodology): “For example, they have implemented Transactional Lock Eli-sion, which is similar to Speculative Lock Elision [58], HyTM [80], SpHT [81], and PhTM [82].”
STAMP: Stanford Transactional Applications for Multi-Processing (2008, methodology): “There have been many proposed designs for TM systems based on hardware (HTM) [6, 16, 29], software (STM) [13, 17, 19, 27, 34], and hybrid hardware/software techniques [8, 12 , 25, 33, 36, 39].”
An effective hybrid transactional memory system with strong isolation guarantees (2007, background): “Hybrid TM: The ﬁrst hybrid TM systems were proposed to address the virtualization challenges of HTM [17, 10].”