The RISC-V Instruction Set Manual

By Andrew Waterman, Yunsup Lee, David A. Patterson, K. Asanovi. 2014

1,409 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/ba52210f8b259a6057132251d03fb96c2dd66b6c

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Citations in the corpus

TensorFlow Lite Micro: Embedded Machine Learning on TinyML Systems (2020, background): “Companies even allow developers to add their own ISA extensions (ARM, 2019; Waterman & Asanovic, 2019).”
The gem5 Simulator: Version 20.0+ (2020, background): “RISC-V is a new ISA which has quickly gained popularity since its creation in 2010, only one year before the initial gem5 release [74].”
HardFails: Insights into Software-Exploitable Hardware Bugs (2019, methodology): “Hence, we use an open-source SoC based on the popular open-source RISC-V [73] architecture as our platform.”
A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices (2016, methodology): “Therefore, we focus on building a micro-architecture based on the RISC-Vinstruction set architecture(ISA)[11] which achieves similar performance and code density to state-of-the art MCUs based on a proprietary ISA, such as ARM Cortex M series cores.”
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices (2017, unknown): “In this section, we will detail the extensions made to the RISC-V ISA and microarchitectural optimizations for increasing the efficiency of the processor core when working in a multicore platform with shared memory.”
The Past, Present and Future of Cyber-Physical Systems: A Focus on Models (2015, methodology): “This architecture is based on the open-source RISC-V [31], is implemented using Chisel [32] and is deployed as an FPGA soft core and a C++ cycle-accurate simulator.”
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology (2019, background): “THE relatively new open instruction set architecture (ISA) RISC-V [1] has already seen a widespread adoption in industry and academia [2]–[5].”
Keystone: an open framework for architecting trusted execution environments (2020, methodology): “We design a reference monitor style security monitor (SM) to enforce TEE guarantees on the platform using four properties of M-mode: (a) it is programmable by platform providers, (b) it meets our needs for a minimal highest privilege mode, (c) it controls hardware delegation of the interrupts and ex”
Komodo: Using verification to disentangle secure-enclave hardware from software (2017, background): “Other examples of a super-privileged restricted environment include DEC Alpha PALcode [24] and RISC-V machine mode [85].”