Enhancement-Mode GaN MIS-HEMTs With n-GaN/i-AlN/n-GaN Triple Cap Layer and High- $k$ Gate Dielectrics

By M. Kanamura, Toshihiro Ohki, T. Kikkawa, K. Imanishi, T. Imada, Atsushi Yamada, Naoki Hara. IEEE Electron Device Letters, 2010

279 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

High-Performance Normally-Off ${\rm Al}_{2}{\rm O}_{3}/{\rm GaN}$ MOSFET Using a Wet Etching-Based Gate Recess Technique (2013, background): “Thus, for power switch applications, it is necessary to combine gate dielectric with gate recess to further scale up the threshold voltage (Vth) and gate swing [5], [6].”
GaN on Si Technologies for Power Switching Devices (2013, background): “semiconductor devices enable high current with normally-off operations, there should remain reliability issues owing to the unstable interface between the GaN and the insulator [24], [25].”
Time-Dependent Failure of GaN-on-Si Power HEMTs With p-GaN Gate (2016, methodology): “Several approaches are being used to achieve e-mode operation: MIS HEMTs [4] with deep gate recess under the gate [5], [6],”
600-V Normally Off ${\rm SiN}_{x}$ /AlGaN/GaN MIS-HEMT With Large Gate Swing and Low Current Collapse (2013, methodology): “A number of techniques, including gate recess [2]–[4], p-type III-nitride gate [5]–[7], fluorine plasma ion implantation [8], and gate-controlled tunnel junction [9] have been proposed and demonstrated to realize normally-OFF operation based on GaN-based heterojunctions.”