Chung-Hsing Hsu
Hardware and Architecture · 2003
A researcher in the Science corpus: 1 paper; trusts 2 researchers and is trusted by 8 researchers here, as inferred from the citation graph.
Subfields
- Hardware and Architecture — 5 citations into it; #588 of 1,551 by trust here, #1,091 by citations
Whom Chung-Hsing Hsu trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
Who trusts Chung-Hsing Hsu overall
Papers from Chung-Hsing Hsu's perspective
Ordered by how strongly the researchers Chung-Hsing Hsu trusts endorse each paper. Same corpus, a different order for every researcher.
- Policies for dynamic clock scheduling (USENIX Symposium on Operating Systems Design and Implementation)
- The design and use of simplePower: a cycle-accurate energy estimation tool (Proceedings - Design Automation Conference)
- The benefits of event: driven energy accounting in power-sensitive systems (ACM SIGOPS European Workshop)
- Design of High-Performance Microprocessor Circuits
- Power: A First-Class Architectural Design Constraint (Computer)
- Energy- and performance-aware mapping for regular NoC architectures (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)
- Route packets, not wires: on-chip interconnection networks (Proceedings - Design Automation Conference)
- Niagara: a 32-way multithreaded Sparc processor (IEEE Micro)
- Clock rate versus IPC: the end of the road for conventional microarchitectures (Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201))
- Demystifying 3D ICs: the pros and cons of going vertical (IEEE Design & Test of Computers)
Their papers
- The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction (2003) — 362 citations