The design and use of simplePower: a cycle-accurate energy estimation tool

By W. Ye, Narayanan Vijaykrishnan, Mahmut Taylan Kandemir, M. J. Irwin. Proceedings - Design Automation Conference, 2000

516 citations recorded by the source corpus.

In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the effect of high-level algorithmic, architectural, and compilation trade-offs on energy. An execution-driven, cycle-accurate RT lev el energy estimation tool that uses transition sensitive energy models forms the cornerstone of this framework. SimplePower also pro vides the energy consumed in the memory system and on-chip buses using analytical energy models. We presen t the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a pow er-conscious post compilation optimization (register relabeling) on the datapath, memory and on-chip bus energy, respectively. We find that these three optimizations reduce the energy by 18-36% in the datapath, 62% in the memory system and 12% in the instruction cache data bus, respectively.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/83e60a73b74fe567151eb6d80290477e272da318

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In Electrical and Electronic Engineering

  1. Sharad Malik
  2. Xinping Zhu
  3. Hangsheng Wang
  4. Eva García-Martín
  5. Lei He
  6. Weiping Liao
  7. Li-Shiuan Peh
  8. Ulrich Kremer

In Hardware and Architecture

  1. Li-Shiuan Peh
  2. Eva García-Martín
  3. Sharad Malik
  4. Ulrich Kremer
  5. Chung-Hsing Hsu
  6. Håkan Grahn
  7. Crefeda Faviola Rodrigues
  8. Graham D. Riley

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