Power: A First-Class Architectural Design Constraint

By T. Mudge. Computer, 2001

562 citations recorded by the source corpus.

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Leakage Current: Moore's Law Meets Static Power (2003, background): “The third equation defines overall power consumption as the sum of dynamic and static power: P = ACV2f + VIleak ( 3 )”
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors (2008, background): “…[24]: Unlike routers based on CMOS technology that must switch with every bit of the transmitted data, leading to a dynamic power dissipation that scales with the bit rate [29], photonic switches switch on and off once per message and their energy dissipation does not depend on the bit rate.”
A self-tuning DVS processor using delay-error detection and correction (2005, background): “Power budgets are even more stringent for battery-operated embedded processors which handle a broad spectrum of applications with diverse energy and performance requirements [7], [14].”
On the Design of a Photonic Network-on-Chip (2007, background): “Electronic NoCs which have many advantages in flexibility and abundant functionality tend to consume high power which scales up with the transmitted bandwidth [22].”