Clock rate versus IPC: the end of the road for conventional microarchitectures

By Vikas Agarwal, M. Hrishikesh, S. Keckler, Doug Burger. Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000

736 citations recorded by the source corpus.

The doubling microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor dock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance-estimating both clock rate and IPC-of an aggressive out-of-order microarchitecture as it is scaled from a 250 nm technology to a 35 nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5% which is far worse than the annual 50-60% to which we have grown accustomed.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/8ce6ebbf99578b8f825d15568e9e17c8d5e480b8

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Citations in the corpus

The New C Standard (Excerpted material) An Economic and Cultural Commentary (2008, positive): “A detailed analysis by Agarwal, Hrishikesh, Keckler, and Burger[3] found that delays caused by the time taken for signals to travel through on-chip wires (12–32 cycles to travel the length of a chip using 35nm CMOS technology, clocked at 10GHz), rather than transistor switching speed, was likely to ”
Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors (2005, background): “In future CMPs, both the processor count and the L2 cache size are likely to increase, with the wire delay reaching tens of clock cycles for cross-chip communication latencies [1, 12].”
The future of wires (2001, background): “These problems will arise because our current architectures are function-centric and implicitly assume that global communication is extremely cheap or free [49], [50].”
Theory of latency-insensitive design (2001, background): “Also, it has been estimated that only a fraction of the chip area between 0.4% and 1.4% will be reachable in one clock cycle [ 9 ].”
An operating system for multicore and clouds: mechanisms and implementation (2010, background): “As the hardware industry is continuously decreasing the size of transistors and increasing their count on a single chip, the chance of faults is rising.”
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures (2000, methodology): “1 m technologies, the long access latencies of a large on-chip L2 cache [1] may be prohibitive for those applications which make use of only a small fraction of the L2 cache.”
Factored operating systems (fos): the case for a scalable operating system for multicores (2009, background): “These servers are designed much in the way that distributed Internet services are designed,but instead of providing high level Internet services, these servers provide traditional kernel services and replace traditionalkernel data structuresinafactored, spatially distributed manner. fos…”
Dynamic branch prediction with perceptrons (2001, background): “Finally, studies have shown that as clock rates increase ove r the next 15 years, wire delays will make large data structure s less feasible [ 1 ].”
Robust non-linear control through neuroevolution (2003, background): “As transistors get smaller and faster, the wires that connect them are becoming much slower, thereby limiting the number of transistors that can be reached in a clock cycle (Agarwal et al. 2000).”
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006, methodology): “At such integration levels, it is imperative to employ parallelism to effectively utilize the transistors [12].”