Demystifying 3D ICs: the pros and cons of going vertical

By W. R. Davis, John M. Wilson, S. Mick, Jian Xu, Hao Hua, C. Mineo, A. Sule, M. Steer, P. Franzon. IEEE Design & Test of Computers, 2005

847 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/aa3c7fbbf9a4c59ee098eafd8b209ea2c0ba82e8

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In Electrical and Electronic Engineering

Citations in the corpus

3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems (2009, background): “Many research groups are exploring its potential applications, such as improving interconnect delay [55]–[60], [93], memory stacks [29], [59], [61], memory-processor or logic–logic stacks [29], [62]–[65], signal-processing circuits [66], [ 67 ], field-programmable gate arrays (FPGAs) [68], [69], ima”
Integrating MEMS and ICs (2015, background): “ion can be categorized into four basic approaches: (1) monolithic MEMS and IC integration using MEMS-first processing, (2) monolithic MEMS and IC integration using interleaved MEMS and IC processing, (3) monolithic MEMS and IC integration using MEMS-last processing via the bulk micromachining of the”
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006, background): “According to [10], the parasitics of inter-tier vias have a small effect on power and delay, because of their small length (i.”
Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems (2011, neutral): “density [16], [17] on a smaller footprint.”
Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits (2014, neutral): “[21–23].”
Hybrid cache architecture with disparate memory technologies (2009, background): “3D ICs have emerged as a promising means to mitigate these interconnect-related problems [9, 16, 29].”
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (2009, background): “The introduction of the three-dimensional (3D) integration technology [9,26] provides the opportunity of stacking memories atop compute cores and therefore alleviates the memory bandwidth challenge of CMPs. Recently, active research [4, 13, 22] has targeted SRAM caches or DRAM memories stacking.”
3-D Topologies for Networks-on-Chip (2006, background): “The power consumption due to this current is described as short-circuit power and is modeled in [28] by (20) where is the average drain current of the nMOS and pMOS devices operating in the saturation region and the value of the coefficients and are described in [29].”
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation (2009, background): “1, 3D ICs, which contain multiple layers of active devices, have the potential for enhancing system performance [7], [8], [9], [10].”