Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks

By Sufi Zafar, A. Callegari, Evgeni P. Gusev, Massimo V. Fischetti. 2003

302 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/fff949176f6eabff24eeadbaab835f56dca9487d

How researchers see this paper

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In Electrical and Electronic Engineering

1. Eduard A. Cartier
2. Evgeni P. Gusev
3. Arvind Kumar
4. Sufi Zafar
5. John F. Conley
6. John Robertson
7. Dieter K. Schroder

Citations in the corpus

• Threshold Voltage Instabilities in High- Gate Dielectric Stacks (2005, methodology): “Understanding the trapped charge stability and the kinetics of discharging are also important to know for modeling the kinetics of charge trapped in the stack [ 44 ].”
• Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks (2005, methodology): “In Section II, sense-and-stress methods were discussed in detail [6], [43], [44].”
• Instabilities in Amorphous Oxide Semiconductor Thin-Film Transistors (2010, background): “tribution [63], or 2) the presence of a distribution of trap capture cross sections, where β relates to the width of distribution [64].”