Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

By Mark L. Green, Evgeni P. Gusev, R. Degraeve, Eric L. Garfunkel. 2001

747 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/e047cf6269a292d8e1fde10df659f5c56f165efe

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Haldun Kufluoglu
2. Dhanoop Varghese
3. Souvik Mahapatra
4. M. A. Alam
5. A. E. Islam
6. Evgeni P. Gusev
7. Sufi Zafar
8. Tibor Grasser

Citations in the corpus

• Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks (2005, background): “This increase in gate leakage current density with scaling is the main motivation for replacing the conventional SiO -based gate dielectrics with higher films [1], [2], [4], [7].”
• A comprehensive model for PMOS NBTI degradation: Recent progress (2007, neutral): “All rights reserved.”