Origami: A Convolutional Network Accelerator

By Lukas Cavigelli, David Gschwend, Christoph Mayer, Samuel Willi, Beat Muheim, Luca Benini. 2015

157 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Vision and Pattern Recognition

1. Vivienne Sze
2. Tien-Ju Yang
3. Yu-hsin Chen
4. Joel S. Emer
5. Song Han
6. Tushar Krishna
7. Luca Benini
8. Yu Wang

In Electrical and Electronic Engineering

1. Tien-Ju Yang
2. Vivienne Sze
3. Yu-hsin Chen
4. Joel S. Emer
5. Tushar Krishna
6. Luca Benini
7. Song Han
8. Wim Dehaene

Citations in the corpus

• CaffePresso: An optimized library for Deep Learning on embedded accelerator-based platforms (2016, background): “While there is significant interest in design of ASICs customized for deep learning [5, 8, 6, 2, 3], along with large FPGA-based [10, 14, 7] and GPU-based accelerators [13] for high-performance systems, we investigate the potential of commercial off-the-shelf SoC hardware for efficiently implementin”
• 14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI (2017, background): “Figure 14.5.6 shows a comparison with recent ConvNet ASICs.”
• A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets (2016, background): “Origami [5], Nvidia Tegra [6], and Eyeriss [7] offer non-optimal embedded solutions, as they keep computational precision constant and do not adapt to varying requirements.”
• YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration (2016, methodology): “I/O power is a primary concern of convolutional accelerators, consuming even more than 30% of the overall chip power [50].”
• Understanding Error Propagation in Deep Learning Neural Network (DNN) Accelerators and Applications (2017, unknown): “[49], nn-X [23], K-Brain [41], Origami [9] ✓ x x”
• Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA (2018, methodology): “It is also proved to be an effective way in the previous work [6], [20], [21] but limited to 16-bit or 12-bit.”
• Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory (2016, background): “While there are architectures that attempt to achieve performance and scalability by reducing the processing units [3]–[5], [7], [8], the overall system performance is often limited due to insufficient memory bandwidth and network latency.”
• Efficient Processing of Deep Neural Networks: A Tutorial and Survey (2017, background): “Other weight stationary examples are found in [84]–[86], [88], [89].”
• Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks (2016, methodology): “[24] present a CNN accelerator for inference that is tested on a four-layer CNN using 7 × 7 filters.”
• A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (2018, background): “Several custom accelerator architectures [76], [78], [83] have been proposed for large convolutional kernels.”
• Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks (2016, background): “Many previous papers have proposed specialized CNN dataflows on various platforms, including GPU [14], FPGA [15] [16] [17] [18] [19] [20] [21], and ASIC [22] [23] [24] [25] [26].”
• Cognitive computation and communication: A complement solution to cloud for IoT (2016, background): “fetches and operations from [33] and [35], with precision”
• YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights (2016, background): “I/O power is a primary concern of convolutional accelerators, consuming even more than 30% of the overall chip power [35].”