YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration

By Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini. 2016

218 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Neurology, Model Architectures, Efficiency & Compression

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Vision and Pattern Recognition

1. Song Han
2. Luc Van Gool
3. Daniel Soudry
4. Yi Yang
5. Dacheng Tao
6. Yoshua Bengio
7. Itay Hubara
8. Trevor Darrell

In Electrical and Electronic Engineering

1. Guoqi Li
2. Kaushik Roy
3. John Paul Strachan
4. R. S. Williams
5. Luca Benini
6. Frank Kagan Gürkaynak
7. Song Han
8. Ran El-Yaniv

In Neurology

1. Yuan Xie
2. Song Han
3. Yoshua Bengio
4. Kaushik Roy

In Model Architectures

1. Song Han
2. Itay Hubara
3. Matthieu Courbariaux
4. Daniel Soudry
5. Ran El-Yaniv
6. Yuan Xie
7. Guoqi Li
8. Kaushik Roy

In Efficiency & Compression

1. Daniel Soudry
2. Itay Hubara
3. Song Han
4. Guoqi Li
5. Luping P. Shi
6. Luca Benini
7. Yuan Xie
8. Yoshua Bengio

Citations in the corpus

• Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations (2016, background): “Andri et al. (2016) even created a hardware implementation to speed up BNNs. Conclusion We have introduced BNNs, which binarize deep neural networks and can lead to dramatic improvements in both power consumption and computation speed.”
• A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (2018, methodology): “ASIC-based accelerators porivde efficiencies on the order of 1000 Gop/sW at reduced precisions, for example Google’s TPU [34] which uses 8 bit arithmetic, or [35] with 1 bit.”
• PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference (2019, background): “Many designs also support optimizations and features including weight pruning and exploiting sparsity [3, 4, 25, 32, 48, 84, 89, 119], reducing precision [8, 62], stochastic computing [65, 90], layer fusing [6], meeting QoS/QoR requirements [108], graph tuning [56], and reconfigurable interconnects ”
• ESPNetv2: A Light-Weight, Power Efficient, and General Purpose Convolutional Neural Network (2018, unknown): “Low-bit representation: Another approach to improve inference of a pre-trained network is low-bit representation of network weights using quantization [1, 9, 20, 39, 47, 57, 64].”
• Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey (2020, background): “If only the weights are binarized/ternarized, the costly MAC operations can be reduced to simpler accumulations [274].”