Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA

By Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Jincheng Yu, Junbin Wang, Song Yao, Song Han, Yu Wang, Huazhong Yang. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018

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SPINN: synergistic progressive inference of neural networks over device and cloud (2020, methodology): “In the rst stage, we exploit the resilience of CNNs to low-precision representation [14, 16, 28, 38] and lower the data precision from 32-bit oating-point down to 8-bit xed-point through linear quantisation [28, 53].”
The Deep Learning Compiler: A Comprehensive Survey (2020, methodology): “DNN Weaver [83], AngelEye [33], ALAMO [63], FP-DNN [32], SysArrayAccel [101] are typical FPGA DL code generator targeting the processor architecture.”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “Kaiyuan et al. [60] proposed a complete design ﬂow, referred to as Angel-Eye, for mapping CNNs onto FPGA.”
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review (2023, methodology): “It is often expressed as giga operations per watt (GOPS/W) or tera operations per watt (TOPS/W), illustrating how many operations the inference engine can perform per watt of power consumption.”