YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights
By Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini. 2016
203 citations recorded by the source corpus.
Convolutional Neural Networks (CNNs) have revolutionized the world of image classification over the last few years, pushing the computer vision close beyond human accuracy. The required computational effort of CNNs today requires power-hungry parallel processors and GP-GPUs. Recent efforts in designing CNN Application-Specific Integrated Circuits (ASICs) and accelerators for System-On-Chip (SoC) integration have achieved very promising results. Unfortunately, even these highly optimized engines are still above the power envelope imposed by mobile and deeply embedded applications and face hard limitations caused by CNN weight I/O and storage. On the algorithmic side, highly competitive classification accuracy canbe achieved by properly training CNNs with binary weights. This novel algorithm approach brings major optimization opportunities in the arithmetic core by removing the need for the expensive multiplications as well as in the weight storage and I/O costs. In this work, we present a HW accelerator optimized for BinaryConnect CNNs that achieves 1510 GOp/s on a corearea of only 1.33 MGE and with a power dissipation of 153 mW in UMC 65 nm technology at 1.2 V. Our accelerator outperforms state-of-the-art performance in terms of ASIC energy efficiency as well as area efficiency with 61.2 TOp/s/W and 1135 GOp/s/MGE, respectively.
Subfields: Computer Vision and Pattern Recognition, Neurology
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Vision and Pattern Recognition
- Vivienne Sze
- Tien-Ju Yang
- Joel S. Emer
- Yu-hsin Chen
- Bashir I. Morshed
- Syed Kamrul Islam
- Jianlin Cheng
- Md Maruf Hossain Shuvo
Citations in the corpus
- Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review (2023, methodology): “For instance, binary values are used for weights in YodaNN [130], and both the weights and activations adopt binary values in BRein [131].”
- Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices (2018, background): “Specialized hardware for binary networks have also been widely explored [20– 24].”
- Efficient Processing of Deep Neural Networks: A Tutorial and Survey (2017, methodology): “YodaNN [133] uses binary weights, while BRein [134] uses binary weights and activations.”
- FINN: A Framework for Fast, Scalable Binarized Neural Network Inference (2016, methodology): “[2] have a similar design as Zhang et al.”
- An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics (2016, background): “This has been exploited in platforms such as YodaNN [57] to reach efficiency in the order of tens of equivalent Top/s/W.”
- Cognitive computation and communication: A complement solution to cloud for IoT (2016, unknown): “binary weights and activations [42][43].”
- Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020, background): “The need for higher speed and efficiency in DNN execution has led to an explosion of DNN accelerators [1, 3, 71–93] that has even made their way to operational datacenters (Google’s TPU [1], NVIDIA T4 [2], Microsoft Brainwave [3], etc.”
- LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks (2017, methodology): “While prior work describes approaches (such as data reuse) to optimize the CNN hardware implementation [28], we keep all the models implemented an unoptimized fashion because our main objective is to compare how constraining weights impacts both computation and memory access energy.”
- CSRNet: Dilated Convolutional Neural Networks for Understanding the Highly Congested Scenes (2018, background): “The additional bonus of using DNNs comes from the enthusiastic hardware community where DNNs are rapidly investigated and implemented on GPUs [13], FPGAs [14, 15, 16], and ASICs [17].”
- Hardware-Software Co-design Approach for Deep Learning Inference (2019, background): “Application Specific Integrated Circuit (ASIC) based implementations have been discussed in [4, 5].”