Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory

By Duckhwan Kim, Jaeha Kung, Sek Meng Chai, Sudhakar Yalamanchili, Saibal Mukhopadhyay. 2016

213 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Electrical and Electronic Engineering

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In Electrical and Electronic Engineering

Citations in the corpus

Supporting Very Large Models using Automatic Dataflow Graph Partitioning (2018, neutral): “Tensor partitioning has been explored by existing work as a means for achieving parallel speedup [8–10] or saving memory access energy [11, 12].”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, background): “Processing-in-memory (PIM) based designs are also proposed to reduce costly off-chip memory accesses [60–63].”
SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks (2018, unknown): “T ETRIS [8] and Neurocube [15] have almost the same compute engines as the previous CNN accelerators.”
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (2018, unknown): “The NeuroCube [36] is based on 16 bit fixed-point MAC units which are capable of performing the necessary computations, but it is unclear if training of modern deep networks converges at this precision and dynamic range.”
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training (2020, background): “Pipelayer [40] and Neurocube [25] proposes ReRAM based acceleration, but does not address scalability and sparsity.”
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing (2019, unknown): “patterns found in fully-connected (FC), convolution (CNN), and recurrent (RNN) neural networks [3], [6]–[8], [11], [12], [15], [17], [18], [24], [33], [36], [40], [47], [53]–[55], [57], [60], [68], [71]–[74], [76], [79], [82].”
RowHammer: A Retrospective (2019, unknown): “, [13]–[15], [18], [22], [24], [34]–[36], [56], [63], [72], [77], [78], [80], [91], [92], [95], [96], [99], [101], [102], [111], [121]–[123], [151], [153], [154], [160], [161], [172], [178], [179], [182], [195], [198], [215]–[219], [221], [222], [228], [257], and [260]).”
Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020, unknown): “The need for higher speed and efficiency in DNN execution has led to an explosion of DNN accelerators [1, 3, 71–93] that has even made their way to operational datacenters (Google’s TPU [1], NVIDIA T4 [2], Microsoft Brainwave [3], etc.”
Machine Learning at Facebook: Understanding Inference at the Edge (2019, unknown): “Recent work on hardware for machine learning and efficient training and inference has substantially advanced the state-of-the-art [41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66].”
A Survey on Federated Learning for Resource-Constrained IoT Devices (2021, unknown): “Apart from this, there is an entire body of works in the domain of neuro-morphic computing [197], [198] dedicated to replicating the extreme power efﬁciency of the human brain by developing new hardware that mimics its synaptic structure.”
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (2017, methodology): “The Neurocube design has demonstrated the feasibility and performance beneﬁts of using HMC for NN accelerators [25].”
The Architectural Implications of Autonomous Driving: Constraints and Acceleration (2018, background): “In addition to computation, prior work also explored novel memory architectures to bring memory closer to processors [1, 12, 38].”
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks (2018, unknown): “Past PIM [2]–[4] solutions tried to move computing logic near DRAM by integrating DRAM with a logic die using 3D stacking [5]–[7].”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, background): “Tetris [4] and Neurocube [11] propose 3-D stacked DNN accelerators to provide high bandwidth for DNN operations.”
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars (2016, background): “Neurocube [31] maps CNNs to 3D high-density high-bandwidth memory integrated with logic, forming a mesh of digital processing elements.”
DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, unknown): “For example, Neurocube achieves 132GOPs [53], while the latest GPU can reach 44TOPs [3].”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, unknown): “The second approach takes advantage of the design of emerging 3D-stacked memory technologies to enable PIM in a more general-purpose manner [7, 34, 35, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 72, 73, 74, 75, 77, 87, 88, 89, 91].”