14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI

By Bert Moons, Roel Uytterhoeven, Wim Dehaene, Marian Verhelst. IEEE International Solid-State Circuits Conference, 2017

400 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/b8242c9d0fb77a125c30d7b92e2e34a468c0d393

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In Computer Vision and Pattern Recognition

In Electrical and Electronic Engineering

Citations in the corpus

A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network (2019, neutral): “In [32], a CNN processor that can run VGG-16 at 1.”
CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks (2019, background): “Recent hardware implementations [5], [9], [16], [19]–[21] for NNs have focused on reduced bit-precisions to achieve”
Neuro-Inspired Computing With Emerging Nonvolatile Memorys (2018, methodology): “To further improve the energy-efficiency, CMOS based ASIC accelerators [10] [12] [13, 14, 15] have been prototyped.”
Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype (2018, background): “Instead, sparse activity (neurons with output 0) can be exploited more easily (Aimar et al., 2017; Moons et al., 2017).”
A TinyML Platform for On-Device Continual Learning With Quantized Latent Replays (2021, background): “ideal target for application-specific HW acceleration [31], [32].”
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices (2018, methodology): “Support for reduced precision has been demonstrated in recent hardware implementations, including Envision [15], Thinker [16], UNPU [17], Loom [18], and Stripes [19].”
Bayesian Bits: Unifying Quantization and Pruning (2020, methodology): “…the fact that commercially available hardware typically only supports efﬁcient computation in power-of-two bit widths (see e.g., Ignatov et al. (2019) for a mobile hardware overview and Moons et al. (2017) for a method to perform four 4-bit multiplications in a 16-bit hardware multiplication unit.)”