Convolution engine: balancing efficiency & flexibility in specialized computing

By Wajahat Qadeer, Rehan Hameed, Ofer Shacham, Preethi Venkatesan, Christos Kozyrakis, Mark A. Horowitz. 2013

204 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Computer Vision and Pattern Recognition, Hardware and Architecture

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Citations in the corpus

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices (2017, unknown): “Also convolutional engines [26]–[28], which outperform general purpose architectures, have been reported.”
MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects (2018, background): “This work also opens up exciting opportunities in compiler designs that can take arbitrary DNNs and map them efficiently over a Maeri-like fabric.”
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture (2019, background): “Many previous papers have developed hardware accelerator architectures that focus on fast and efficient execution of DL inference [2, 13, 15, 30, 51, 52, 57, 59, 61].”
RedEye: Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision (2016, background): “Improving upon these, some accelerators exploit data locality for performance and efficiency of ConvNet processing [33]–[35].”
MachSuite: Benchmarks for accelerator design and customized architectures (2014, background): “While this effect shows up in benchmarks for conventional platforms, accelerators are more Research Area Publications Acc-Centric [11], [12], [13], [14], [15], [16], [21] Architectures [22], [34], [37], [40], [41], [43], [46] HLS Optimizations [4], [6], [7], [17], [20], [23], [31], [32], [33], [35],”
Fused-layer CNN accelerators (2016, background): “In [14], the authors proposed a generalized convolution engine that can be used for various computer vision and computational photography algorithms which have convolutionlike data-flow patterns.”
From high-level deep neural models to FPGAs (2016, background): “[25] propose Convolution Engine which reduces the number of operations required in convolution layers.”
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration (2016, methodology): “BinaryConnect is a method which trains a deep neural network with binary weights during the forward and backward propagation, while retaining the precision of the stored weights for gradient descent optimization.”
YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights (2016, methodology): “nn-X (NeuFlow) [34] FPGA Zynq XC7Z045 227 227 200 d:4000 25 fixed16 ConvEngine [14] synth.”
A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices (2016, background): “Also convolutional engines[26]–[28] which outperform general purpose architectures have been reported.”
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks (2016, background): “Before CNNs became mainstream, there was already research on high-efficiency convolution due to its wide applicability in image signal processing (ISP) [40].”
DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning (2014, background): “However, the aforementioned trends have already been identified by a number of researchers who have proposed accelerators implementing Convolutional Neural Networks [3] or Multi-Layer Perceptrons [38]; accelerators focusing on other domains, such as image processing, also propose efficient implement”
DaDianNao: A Machine-Learning Supercomputer (2014, background): “Accelerators for video compression [21], image convolutions [44], libraries or specific workloads [49], [17] have been proposed.”