Fused-layer CNN accelerators

By Manoj Alwani, Han Chen, Michael Ferdman, Peter Milder. Micro, 2016

668 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/72ed74f00d0f7312f7ed96d93ed43f0052d526bc

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In Artificial Intelligence

In Computer Vision and Pattern Recognition

In Electrical and Electronic Engineering

Citations in the corpus

A survey of FPGA-based accelerators for convolutional neural networks (2018, methodology): “To exploit this, they use circular line buffer for every layer, which achieves data reuse with lower complexity and less BRAM resources than the tile-based buffer used by Alwani et al. [78].”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, neutral): “Neuﬂow [51], Eyeriss [52–54], Flexﬂow [55], Fused-CNN [56], CNN-Paritition [57], GANAX [58], UCNN [59], TANGRAM [131], Sparse-Systolic [132], MAERI [133]”
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection (2019, background): “Moreover, designs in [6], [11], and [14] use doubled buffer to pipeline the computation.”
CompAct (2019, background): “We note that for CNNs, convolution layers account more than 90% of the computational load and therefore dominate energy consumption [2, 26, 28].”
DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters (2018, methodology): “Layer fusion techniques have been previously applied to CNN accelerators [17].”
A Configurable Cloud-Scale DNN Processor for Real-Time AI (2018, background): “There has been a large body of research in DNN accelerators targeting FPGAs, in particular for accelerating Convolutional Neural Networks (CNNs), such as [42], [63]–[94].”
Inducing and Exploiting Activation Sparsity for Fast Neural Network Inference (2020, methodology): “Reference (Gudovskiy et al., 2018) proposed a projection technique coupled with non-linear dimensionality reduction, which required modifying the network structure, while (Alwani et al., 2016) proposed to stochastically prune activations as an adversarial defense.”
Accelerating Convolutional Neural Networks via Activation Map Compression (2018, background): “them, which can reduce the number of MAC’s performed. However, their method also modiﬁes the network structure and in addition, it does not increase the sparsity of the activation maps. Alwani et al. [3] reduce the memory requirement of the network by recomputing activation maps instead of storing t”
Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer (2017, background): “2, because the early convolutional layers have very few weights [19], thus reusing them makes little difference.”
Maximizing CNN accelerator efficiency through resource partitioning (2016, methodology): “[2] uses a fused-layer technique to reduce bandwidth use of convolutional layers.”
MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects (2018, neutral): “It also contains comparators for pooling operations.”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, background): “Due to their insatiable demand for compute power, naturally, both the research community [1–28] as well the industry [29–31] have turned to accelerators to accommodate modern DNN computation.”
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture (2019, background): “Tile-based architectures have frequently been proposed for deeplearning accelerator designs [1, 2, 13, 15, 22, 25, 30, 42, 51, 53, 56, 58, 61, 75].”
SCNN: An accelerator for compressed-sparse convolutional neural networks (2017, background): “propose to fuse adjacent layers in a dense CNN accelerator so that intermediate activations between layers can be kept on chip [2].”
Convergence of Edge Computing and Deep Learning: A Comprehensive Survey (2019, methodology): “, CNN, a finer grid partitioning can be applied to minimize communication, synchronization, and memory overhead [130].”
HarDNet: A Low Memory Traffic Network (2019, background): “In contrast, fused-layer computation for multiple convolutional layers has been proposed [1], in which intermediate layers in a fused-layer group will not produce any memory traffic for feature maps.”
Timeloop: A Systematic Approach to DNN Accelerator Evaluation (2019, background): “Future work includes modeling inter-layer relationships to ﬁnd globally-optimal solutions for full networks (as in [2]).”