From high-level deep neural models to FPGAs

By Hardik Sharma, Jongse Park, Divya Mahajan, Emmanuel Amaro, Joon Kyung Kim, Chenkai Shao, Asit K. Mishra, Hadi Esmaeilzadeh. Micro, 2016

500 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/924d6c44fda59dc9ac1f25d7cc12d669c5f9e557

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In Artificial Intelligence

In Computer Vision and Pattern Recognition

In Hardware and Architecture

Citations in the corpus

DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, background): “• Neural Network Accelerators: Lots of designs that accelerate NN applications with various platforms (ASIC, GPU, FPGA) [22, 39, 48, 83, 92] have been proposed.”
The Deep Learning Compiler: A Comprehensive Survey (2020, methodology): “the DL models to PUs and PEs. All these parameters are usually determined by the design space exploration using various strategies, such as combining the performance model and auto-tuning. DNN Weaver [83], AngelEye [33], ALAMO [63], FP-DNN [32], SysArrayAccel [101] are typical FPGA DL code generator”
SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks (2018, background): “On average, the computation of fully-connected layers accounts for ≈ 1% of the total number of computations performed in CNNs [2], [3], [8].”
Machine Learning at Facebook: Understanding Inference at the Edge (2019, background): “Recent work on hardware for machine learning and efficient training and inference has substantially advanced the state-of-the-art [41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77].”
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration (2019, unknown): “For example, DNN application practitioners would prefer that the hardware programming environment be hidden by DNN development frameworks like PyTorch or TVM so that they don’t need to worry about low-level development details, as in the case of VTA [1] and DNNWeaver [23].”
Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020, background): “The need for higher speed and efficiency in DNN execution has led to an explosion of DNN accelerators [1, 3, 71–93] that has even made their way to operational datacenters (Google’s TPU [1], NVIDIA T4 [2], Microsoft Brainwave [3], etc.”
Timeloop: A Systematic Approach to DNN Accelerator Evaluation (2019, background): “A few recent proposals have attempted this challenging task [19], [27], [34], [38].”
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach (2018, background): “DNN accelerators achieve high performance by exploiting parallelism over hundreds of processing elements (PEs) and high energy efficiency by maximizing data reuse within PEs and on-chip scratchpads [1, 9, 11, 19, 31, 38].”
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review (2023, methodology): “Frameworks such as DNNWeaver [414], DNNBuilder [415], T2S-Tensor [416], and HeteroCL [417] have been developed recently for FPGA, ASIC, and other DL hardware accelerators for efﬁcient EI.”
Maximizing CNN accelerator efficiency through resource partitioning (2016, methodology): “[24] and [30] propose complete frameworks for generating FPGAbased accelerators from CNN specifications.”
SPINN: synergistic progressive inference of neural networks over device and cloud (2020, methodology): “6 SPINN uses these IDs to build an execution graph in the form of a directed acyclic graph (DAG), with nodes representing tensor operations and edges the tensor flows among them [1, 62, 75].”
TVM: An Automated End-to-End Optimizing Compiler for Deep Learning (2018, background): “Figure 21 breaks down ResNet inference time into CPU-only execution and CPU+FPGA execution.”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, unknown): “…Embedded-FPGA-CNN [35], FPGA-Exploration [36], OpenCL-FPGA-CNN [37] [126], Caffeine [38], DeepBurning [39], FPGA-DPCNN [40], TABLA [41], DNNWEAVER [42], FP-DNN [43], FPGA-LSTM [44], ESE [45], FPGA-Dataﬂow [46], FPGA-BNN [47], FPGA-Utilization [48], FFT-CNN [49], VIBNN [50], iSwitch [127],…”
The Architectural Implications of Autonomous Driving: Constraints and Acceleration (2018, background): “FPGAs have been discussed as another alternative, which also provide high performance and energy eiciency with the additional capability of reconiguring the fabric programmatically [19, 42, 63].”