Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

By Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank Kagan Gürkaynak, Luca Benini. 2017

69 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Antonio Loquercio
2. Davide Scaramuzza
3. Daniele Palossi
4. Luca Benini
5. Francesco Conti
6. Eric Flamand
7. Henri Rebecq
8. Guillermo Gallego

In Hardware and Architecture

1. Luca Benini
2. Daniele Palossi
3. Giovanni De Micheli
4. Srinivasan Murali

Citations in the corpus

• A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones (2018, methodology): “The FC uses an in-order, DSP-extended four-stage microarchitecture implementing the RISC-V instruction set architecture [32].”
• The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology (2019, background): “Since the speed of Ariane is higher than the speed reported for the embedded profile core, and its IPC is comparable [6], we conclude that execution time is lower, although less energy efficient when comparing only the baseline RISCV ISA.”