MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects
By Hyoukjun Kwon, A. Samajdar, Tushar Krishna. International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
447 citations recorded by the source corpus.
Deep neural networks (DNN) have demonstrated highly promising results across computer vision and speech recognition, and are becoming foundational for ubiquitous AI. The computational complexity of these algorithms and a need for high energy-efficiency has led to a surge in research on hardware accelerators. % for this paradigm. To reduce the latency and energy costs of accessing DRAM, most DNN accelerators are spatial in nature, with hundreds of processing elements (PE) operating in parallel and communicating with each other directly. DNNs are evolving at a rapid rate, and it is common to have convolution, recurrent, pooling, and fully-connected layers with varying input and filter sizes in the most recent topologies.They may be dense or sparse. They can also be partitioned in myriad ways (within and across layers) to exploit data reuse (weights and intermediate outputs). All of the above can lead to different dataflow patterns within the accelerator substrate. Unfortunately, most DNN accelerators support only fixed dataflow patterns internally as they perform a careful co-design of the PEs and the network-on-chip (NoC). In fact, the majority of them are only optimized for traffic within a convolutional layer. This makes it challenging to map arbitrary dataflows on the fabric efficiently, and can lead to underutilization of the available compute resources. DNN accelerators need to be programmable to enable mass deployment. For them to be programmable, they need to be configurable internally to support the various dataflow patterns that could be mapped over them. To address this need, we present MAERI, which is a DNN accelerator built with a set of modular and configurable building blocks that can easily support myriad DNN partitions and mappings by appropriately configuring tiny switches. MAERI provides 8-459% better utilization across multiple dataflow mappings over baselines with rigid NoC fabrics.
Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/5f0da3cedda449b72fe36fa78798651a038f515c
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Vision and Pattern Recognition
- Tushar Krishna
- Joel S. Emer
- Yu-hsin Chen
- Sheng-Chun Kao
- Hyoukjun Kwon
- Angshuman Parashar
- David M. Brooks
- S. Keckler
In Electrical and Electronic Engineering
- Tushar Krishna
- Joel S. Emer
- Yu-hsin Chen
- Sheng-Chun Kao
- Hyoukjun Kwon
- Angshuman Parashar
- S. Keckler
- David M. Brooks
Citations in the corpus
- Domain-specific Genetic Algorithm for Multi-tenant DNNAccelerator Scheduling (2021, methodology): “This enables the sub-accelerator to run various dataflows or mappings [57].”
- Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020, background): “MAERI [52] and SIGMA [95] propose a reconfigurable interconnect among the PEs to deal with sparsity in neural networks [52] and matrix multiplications [95] and to”
- DeepStore: In-Storage Acceleration for Intelligent Queries (2019, methodology): “DNN Accelerator: Several accelerator designs have been proposed to speed up the training and inference computation of popular DNN models [28, 29, 34, 44, 49, 50, 52, 60, 65, 68, 71, 75, 78].”
- Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review (2023, unknown): “MAERI allows flexible dataflow through reconfigurable interconnects, distribution trees, and adder trees.”
- AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, unknown): “Dataflow Neuflow [51], Eyeriss [52–54], Flexflow [55], Fused-CNN [56], CNN-Paritition [57], GANAX [58], UCNN [59], TANGRAM [131], Sparse-Systolic [132], MAERI [133]”
- Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach (2018, methodology): “We validated MAESTRO’s performance model against RTL simulations of two accelerators - MAERI [24] and Eyeriss [13] when running VGG16 and AlexNet respectively1.”
- MASR: A Modular Accelerator for Sparse RNNs (2019, methodology): “Beyond accelerators for DNNs and CNNs, other work has investigated RNNs, and search algorithms for ASR and machine translation [31], [35], [36], [37], [38], [39], [40].”
- Timeloop: A Systematic Approach to DNN Accelerator Evaluation (2019, background): “There is an abundance of excellent recent work on DNN accelerators [6], [13], [22], [26], [27], [32], [35]–[37].”