A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices

By Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank Kagan Gürkaynak, Luca Benini. 2016

409 citations recorded by the source corpus.

Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also need to be flexible in their computing capabilities, from a few kOPS to GOPS. Near-threshold(NT) operation can achieve higher energy efficiency, and the performance scalability can be gained through parallelism. In this paper we describe the design of an open-source RISC-V processor core specifically designed for NT operation in tightly coupled multi-core clusters. We introduce instruction-extensions and microarchitectural optimizations to increase the computational density and to minimize the pressure towards the shared memory hierarchy. For typical data-intensive sensor processing workloads the proposed core is on average 3.5x faster and 3.2x more energy-efficient, thanks to a smart L0 buffer to reduce cache access contentions and support for compressed instructions. SIMD extensions, such as dot-products, and a built-in L0 storage further reduce the shared memory accesses by 8x reducing contentions by 3.2x. With four NT-optimized cores, the cluster is operational from 0.6V to 1.2V achieving a peak efficiency of 67MOPS/mW in a low-cost 65nm bulk CMOS technology. In a low power 28nm FDSOI process a peak efficiency of 193MOPS/mW(40MHz, 1mW) can be achieved.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

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Citations in the corpus

A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones (2018, neutral): “DSP-extended four-stage microarchitecture implementing the RISC-V instruction set architecture [32].”
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (2018, methodology): “We combine a general purpose RISC-V processor core [6] with multiple NTX FP streaming co-processors.”
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology (2019, background): “However, the ISA extensions proposed in [6] such as postincrementing load and stores, hardware loops, and single instruction multiple data (SIMD) capability show a speedup of up to 10× compared to the baseline ISA.”
Ultra low-power visual odometry for nano-scale unmanned aerial vehicles (2017, methodology): “The PULP cluster has 4 optimized RISCV cores [12] featuring several enhancements with respect to the reference implementation, including a register-register multiply-accumulate instruction, vectorized instructions for several data types, two hardware loops and support for unaligned load/store operat”
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics (2016, methodology): “The four OR10N cores are based on an in-order, singleissue, four stage pipeline, implementing the OpenRISC [14] instruction set architecture (ISA), improved with extensions for higher throughput and energy efficiency in parallel signal processing workloads [15].”