DRISA: A DRAM-based Reconfigurable In-Situ Accelerator

By Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie. Micro, 2017

446 citations recorded by the source corpus.

Data movement between the processing units and the memory in traditional von Neumann architecture is creating the “memory wall” problem. To bridge the gap, two approaches, the memory-rich processor (more on-chip memory) and the compute-capable memory (processing-in-memory) have been studied. However, the first one has strong computing capability but limited memory capacity/bandwidth, whereas the second one is the exact the opposite.To address the challenge, we propose DRISA, a DRAM-based Reconfigurable In-Situ Accelerator architecture, to provide both powerful computing capability and large memory capacity/bandwidth. DRISA is primarily composed of DRAM memory arrays, in which every memory bitline can perform bitwise Boolean logic operations (such as NOR). DRISA can be reconfigured to compute various functions with the combination of the functionally complete Boolean logic operations and the proposed hierarchical internal data movement designs. We further optimize DRISA to achieve high performance by simultaneously activating multiple rows and subarrays to provide massive parallelism, unblocking the internal data movement bottlenecks, and optimizing activation latency and energy. We explore four design options and present a comprehensive case study to demonstrate significant acceleration of convolutional neural networks. The experimental results show that DRISA can achieve 8.8× speedup and 1.2× better energy efficiency compared with ASICs, and 7.7× speedup and 15× better energy efficiency over GPUs with integer operations.CCS CONCEPTS• Hardware → Dynamic memory; • Computer systems organization → reconfigurable computing; Neural networks;

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/4d61c115fc70ee8abfec80214c11c8a54e72e98a

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Citations in the corpus

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks (2018, background): “Solutions which change DRAM bit-cell are possible but come with 2-3× higher area overheads [30], [31].”
RowHammer: A Retrospective (2019, unknown): “, [13]–[15], [18], [22], [24], [34]–[36], [56], [63], [72], [77], [78], [80], [91], [92], [95], [96], [99], [101], [102], [111], [121]–[123], [151], [153], [154], [160], [161], [172], [178], [179], [182], [195], [198], [215]–[219], [221], [222], [228], [257], and [260]).”
Memory devices and applications for in-memory computing (2020, methodology): “In DRAM, simultaneous reading of devices along multiple rows can be used to execute basic Boolean functions within the memory array 16,17 .”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “These substrates can perform bulk bitwise operations in a special DRAM array augmented with computational circuitry [90] and in PCM [78].”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, unknown): “Neurocube [60], XNOR-POP [61], DRISA [62], 3DICT [63], NAND-NET [134], SCOPE [135], Promise [136] Light Models EIE [64], SC-DCNN [65], SCNN [66], Escher [67], LookNN [68], Bit-Pragmatic DNN [69], Bit Fusion [70], Cn-vlutin [99], TIE [137], Laconic [138], ADM-NN [139], Gist [140] Co-Design DPS-CNN…”