Cache-Conscious Wavefront Scheduling
By Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt. Micro, 2012
422 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/6a9d7c4d41a790b7039282aa5f69c7074bd570ff
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Onur Mutlu
- Saugata Ghose
- Rachata Ausavarungnirun
- Adwait Jog
- Carole-Jean Wu
- Akhil Arunkumar
- Christopher J. Rossbach
- Timothy G. Rogers
In Hardware and Architecture
- Onur Mutlu
- Saugata Ghose
- Rachata Ausavarungnirun
- Adwait Jog
- Christopher J. Rossbach
- Jayneel Gandhi
- Vance Miller
- Joshua Landgraf
Citations in the corpus
- Accel-Sim: An Extensible Simulation Framework for Validated GPU Modeling (2018, background): “The Polybench workloads are cache capacity sensitive [59].”
- Understanding the Future of Energy Efficiency in Multi-Module GPUs (2019, background): “…techniques such as locality aware thread-block (CTA) scheduling and data placement [5], [44], sophisticated cache management strategies [8], [45], [46], [47], [48], [49], [50], and data compression techniques [51], [52], [53], [54], need to be re-applied not just within today’s GPUs, but…”
- Zorua: A holistic approach to resource virtualization in GPUs (2016, methodology): “Our decoupled design allows this challenge to be addressed independently from the coordinator using more intelligent scheduling algorithms [36, 50, 58] and cache management schemes [3, 44, 45, 78].”
- MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (2018, background): “[105] explore a TLB design for heterogeneous CPUGPU systems, and add TLB awareness to the existing CCWS GPU warp scheduler [112].”