Dynamic branch prediction with perceptrons

By Daniel A. Jiménez, Calvin Lin. Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, 2001

505 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/948b7d8d921dd709649c1efa53ebbf2af835d89e

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Citations in the corpus

Meltdown: Reading Kernel Memory from User Space (2018, background): “More recently, ideas to use neural branch prediction [62, 38, 60] have been picked up and integrated into CPU architectures [9].”
Learning Execution through Neural Code Fusion (2019, methodology): “Highperformance modern microprocessors commonly include perceptron [23] or table-based branch predictors that memorize commonly taken paths through code [36].”
Socio-Technological Challenges and Opportunities: Paths Forward (2021, background): “…1967, Smith, 1982a, Hwu and Patt, 1986], branch predictors [Smith, 1981, Lee and Smith, 1984, Pnevmatikatos et al., 1993, Yeh et al., 1993, Jimenez and Lin, 2001], caches [Smith, 1982b, Hill, 1988, Przybylski et al., 1989, Jouppi, 1990], prefetchers [Baer and Chen, 1991, Fu et al., 1992,…”
Runahead execution: an alternative to very large instruction windows for out-of-order processors (2003, methodology): “Processor Frequency 4 GHz 8 GHz Fetch/Issue/Retire Width 3 6 Branch Misprediction Penalty 29 stages 58 stages Instruction window size 128 512 Scheduling window size 16 int, 8 mem, 24 fp 64 int, 32 mem, 96 fp Load and store buffer sizes 48 load, 32 store 192 load, 128 store Functional units 3 int, 2 ”
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach (2008, background): “Jimenez and Lin [19] propose the perceptron branch predictor, which outperforms tablebased prediction schemes by significant margins.”
BranchScope: A New Side-Channel Attack on Directional Branch Predictor (2018, background): “Modern branch predictors [15, 31, 41, 43, 50] are typically implemented as a composition of a simple one-level bimodal predictor indexed directly by the program counter (we refer to it as the 1-level predictor [49]), and a gshare-style 2-level predictor [57].”