NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs]

By Anand T. Krishnan, Vijay Reddy, Srinivasan Chakravarthi, John Rodriguez, Soji John, S. Krishnan. IEEE International Electron Devices Meeting 2003, 2003

193 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/748a7d2357f0c0223f7e7ac9189875402528bce3

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In Electrical and Electronic Engineering

Citations in the corpus

Impact of NBTI on SRAM read stability and design for reliability (2006, methodology): “However, in order to account for the fact that trap generation causes mobility degradation which further leads to threshold voltage degradation [4], the above equation is modified as”
Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation (2008, background): “Recently, the interest of NBTI community has been gradually elevated to characterizing impacts of NBTI on digital-circuit reliability [69], [70], [86]‐[ 89 ] and on analog and RF circuit reliability [90]‐[92].”
A two-stage model for negative bias temperature instability (2009, methodology): “The recorded OTF degradation in IDlin was converted to ΔV OTF th using the simple expression ΔV OTF th ≈ (VG − Vth0)(ID − ID0)/ID0 [9, 10].”
A Comparative Study of Different Physics-Based NBTI Models (2013, methodology): “V measurements (measure–stress–measure (MSM) method), to obtain degradation of device parameters such as ΔVT [2]–[4], [15], Δgm [2], ΔS [3], and ΔIDLIN and ΔIDSAT [15]; it is now well known that this approach suffers from recovery-related artifacts [24] due to large measurement (stress-off) time (ap”
Impact of NBTI on the temporal performance degradation of digital circuits (2005, background): “The delay of a gate can be approximately expressed as [7] and [8]”