New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

By Yu Cao, Takashi Sato, Michael Orshansky, D. Sylvester, Chenming Calvin Hu. Proceedings of the IEEE Custom Integrated Circuits Conference, 2000

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New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration (2006, methodology): “An improved predictive method was developed by the Berkeley Predictive Technology Model (BPTM) [3].”
Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design (2004, methodology): “We have used 65-nm node calibrated BSIM [ 25 ] model to simulate the MOS devices.”
New generation of predictive technology model for sub-45nm design exploration (2006, methodology): “As compared to previous BPTM, the new predictive methodology has better physicality and scalability over a wide range of process and design conditions.”
Gate sizing to radiation harden combinational logic (2006, methodology): “The SPICE libraries for four process technologies—180, 130, 100, and 70 nm—were obtained from the Berkeley Predictive Technology Model [ 3 ].”
Impact of NBTI on SRAM read stability and design for reliability (2006, methodology): “We perform transistor level simulations using BPTM 70nm and 100nm models [10], [ 11 ], with shifted model files to simulate the effect of NBTI on PMOS devices.”
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers (2009, methodology): “18μm BSIM3 models [43], thermal noise is calculated based on 0.”