New generation of predictive technology model for sub-45nm design exploration

By Wei Zhao, Yu Cao. IEEE International Symposium on Quality Electronic Design, 2006

555 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/8b0b2f2605e533c40cac32e1a3a989f7aa759841

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In Electrical and Electronic Engineering

Citations in the corpus

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM (2007, methodology): “Using predictive technology models, the proposed ST bitcell is compared with the 6T cell to verify the effectiveness of our technique in scaled technologies [17].”
Modeling and minimization of PMOS NBTI effect for robust nanometer design (2006, unknown): “Technology specifications are taken from the Predictive Technology Model [18].”
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region (2007, background): “6 aF with 18-nm physical gate length, which is about 4% of the bulk CMOS gate capacitance (predictive Berkeley short-channel IGFET model [30]–[32]) with a minimum gate width (48 nm) at the 32-nm node.”
3-D Topologies for Networks-on-Chip (2006, background): “Tradeoffs in determining these topologies are discussed and the impact of the network parameters on the resulting optimum topologies are evaluated for various network sizes.”
VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects (2008, methodology): “We find the value for these parameters by fitting the leakage Equation 5 to experimental data for the 32 nm technology node obtained from SPICE simulations using the Predictive Technology Model [37].”
A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking (2007, background): “[28]–[30]), the CNFET shows better single device performance based on the intrinsic CV/I gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET (where C is the intrinsic gate capacitance) in the 32-nm node, even with device nonidealities (Table I).”
Process Variation Tolerant 3T1D-Based Cache Architectures (2007, methodology): “All Hspice simulations for the three technology nodes are based on Predictive Technology Models (PTM) [32].”