New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration

By Wei Zhao, Yu Cao. IEEE Transactions on Electron Devices, 2006

856 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/51db58e17d061db3e03bf43ebec5c9cd6569259f

How researchers see this paper

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In Electrical and Electronic Engineering

1. Onur Mutlu
2. H. Philip Wong
3. Jie Deng
4. Jeremie S. Kim
5. Donghyuk Lee
6. Wenping Wang
7. Vivek Seshadri
8. Subhasish G. Mitra

Citations in the corpus

• Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (2017, methodology): “We implement the sense amplifier using 55nm DDR3 model parameters [14], and PTM low-power transistor models [9, 117].”
• Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits (2009, methodology): “The CNFET inverters were simulated using a CNFET SPICE model [1], [2], [10], while the silicon CMOS inverters were simulated using the BSIM4 predictive technology models7 [13], [14].”
• The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis (2010, methodology): “A 65-nm predictive technology model (PTM) [ 23 ] is used in the simulation.”
• Silicon-photonic clos networks for global on-chip communication (2009, methodology): “For this work we use the 22 nm predictive technology models [16] and interconnect projections from [6] and the ITRS.”