Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design
By Santanu Mahapatra, Vaibhav Vaish, Christoph Wasshuber, Kaustav Banerjee, A. M. Ionescu. IEEE Transactions on Electron Devices, 2004
153 citations recorded by the source corpus.
A physically based compact analytical single electron transistor (SET) model is proposed for hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the "orthodox theory" of single electron tunneling, and valid for single or multi gate, symmetric or asymmetric devices and can also explain the background charge effect. The model parameters are physical device parameters and an associated parameter extraction procedure is reported. The device characteristics produced by the proposed model are verified with Monte Carlo simulation for large range of drain to source voltages (|V/sub DS/|/spl les/3e/C/sub /spl Sigma//) and temperatures [T/spl les/e/sup 2//(10k/sub B/C/sub /spl Sigma//)] and good agreements are observed. The proposed model is implemented in a commercial circuit simulator in order to develop a computer-aided design framework for CMOS-SET hybrid IC designs. A series of SPICE simulations are successfully carried out for different CMOS-SET hybrid circuits in order to reproduce their experimental/Monte Carlo simulated characteristics.
Subfields: Atomic and Molecular Physics, and Optics, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/5ea9b0c2f6c66d2fd1316f937bd4f82382da55c5
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In Electrical and Electronic Engineering
Citations in the corpus
- Towards atomic and close-to-atomic scale manufacturing (2019, background): “However, the number of functional devices developed is still quite limited, although we have witnessed the conception and demonstration of the singleatom transistor [93] or single-electron transistor [134].”