PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning

By Linghao Song, Xuehai Qian, Hai Helen Li, Yiran Chen. International Symposium on High-Performance Computer Architecture, 2017

775 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/6b3c06f148deba3926eff3c22ddf4dfd1195ac8a

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Vision and Pattern Recognition

In Electrical and Electronic Engineering

Citations in the corpus

Machine Learning at Facebook: Understanding Inference at the Edge (2019, background): “Recent work on hardware for machine learning and efficient training and inference has substantially advanced the state-of-the-art [41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77].”
Hardware implementation of memristor-based artificial neural networks (2024, positive): “Alternatives to overcome this lim-itationhavebeenproposed,asforinstancethesimulatordevelopedby Song et al. 246 to evaluate their PipeLayer architecture, which considers highly parallel designs based on the notion of parallelism granularity and weight replication.”
Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020, background): “The need for higher speed and efficiency in DNN execution has led to an explosion of DNN accelerators [1, 3, 71–93] that has even made their way to operational datacenters (Google’s TPU [1], NVIDIA T4 [2], Microsoft Brainwave [3], etc.”
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration (2019, background): “Based on these architecture templates, recent advances have also started exploring how to leverage application’s sparsity patterns [18]–[20] and/or emerging in-memory computing technology [21], [22].”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, methodology): “ISAAC [26], PipeLayer [28], and Prime [27] use resistive RAM (ReRAM) for accelerating DNNs.”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, methodology): “TETRIS [85], RENO [88], PRIME [86], ISAAC [87], Memristive Boltzmann Machine [89], PipeLayer [90], Atom-layer [91], ReCom [92], ReGAN [93], ReRAM ACC.”
Memory devices and applications for in-memory computing (2020, background): “Although the high parallelism provided by this approach is promising, its implementation is hardwired and therefore not scalable, and requires very precise conductance tuning and high linearity of current–voltage characteristics.”
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture (2019, background): “Tile-based architectures have frequently been proposed for deeplearning accelerator designs [1, 2, 13, 15, 22, 25, 30, 42, 51, 53, 56, 58, 61, 75].”
Neuro-inspired computing chips (2020, methodology): “With inter-layer parallelism and weight replication, a continuous dataflow can be achieved by balancing the execution time of different layers 70 .”
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training (2020, background): “Pipelayer [40] and Neurocube [25] proposes ReRAM based acceleration, but does not address scalability and sparsity.”
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation (2019, background): “However, application to larger DNNs has yet to be demonstrated, though numerous neuromorphic proposals have leveraged eNVMs, particularly using RRAMs for processing-in-memory architectures [5, 11, 61, 64].”