PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture

By Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi. International Symposium on Computer Architecture, 2015

543 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/ba8dcc218ed86364208623c2d280089a7acefa4a

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Citations in the corpus

Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory (2016, background): “There have been proposals for off-loading data-intensive operations onto the logic die [24]–[26].”
DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, background): “• Processing-in-Memory Architectures: On one hand, there is plenty of recent work on PIM [10, 12, 16, 18, 20, 30, 32, 34, 36, 42, 46, 52, 53, 67, 73, 73, 75, 76, 88, 93, 95] that built lightweight processors, reconfigurable or application-specific logics in the logic die of HMC [74] or HBM [58].”
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing (2019, unknown): “We focus on DIMM-based near-memory processing [8], [23], [74] instead of resorting to specialized 2.5D/3D integration processes (e.g. HBM) [37], [39], [41].”
GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks (2017, background): “• U-PEI: This configuration enables instruction offloading by following a mechanism similar to PEI [14] except that we assume perfect locality-aware offloading and ideal coherence management.”
Compute Caches (2017, methodology): “This can be accomplished using recent advancements in 3D die-stacking [8].”
Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories (2016, background): “Based on the PAs, the dynamic linked driver library ﬁrst optimizes and reschedules the operation requests, and then issues extended instruction for PIM [3].”
RowHammer: A Retrospective (2019, unknown): “, [13]–[15], [18], [22], [24], [34]–[36], [56], [63], [72], [77], [78], [80], [91], [92], [95], [96], [99], [101], [102], [111], [121]–[123], [151], [153], [154], [160], [161], [172], [178], [179], [182], [195], [198], [215]–[219], [221], [222], [228], [257], and [260]).”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “thein-memoryGPUcores. This scheduling technique improves performance and energy eﬃciency by an average of 42% and 27%, respectively. 5.2.4. PEI: PIM-Enabled Instructions PIM-EnabledInstructions (PEI) [35] aims to provide the minimal processing-in-memory support to take advantageofPIMusing3D-stackedm”