TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory

By Mingyu Gao, Jing Pu, Xuan S. Yang, Mark A. Horowitz, Christos Kozyrakis. International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

561 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/733a765e1f54eb86dbaabe03d7ba66d72363f665

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Citations in the corpus

SCNN: An accelerator for compressed-sparse convolutional neural networks (2017, background): “These data halos [13] can be resolved in one of two ways:”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, methodology): “Second, energy consumption for DNN acceleration is usually dominated by data accesses to the on-chip storage and off-chip memory [1, 3, 4].”
Beyond Data and Model Parallelism for Deep Neural Networks (2018, background): “Gao et al. (2017; 2019) exploited hybrid parallelization on tiled domain-specific hardware and proposed various dataflow optimizations for both intra-layer and inter-layer data communication.”
DeepStore: In-Storage Acceleration for Intelligent Queries (2019, methodology): “DNN Accelerator: Several accelerator designs have been proposed to speed up the training and inference computation of popular DNN models [28, 29, 34, 44, 49, 50, 52, 60, 65, 68, 71, 75, 78].”
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (2018, background): “Near-memory inference architectures embedded in the logic die of an HMC have also been investigated, for example the 2D accelerator array presented in [18] which uses 16 bit fixed-point arithmetic and achieves up to 450 Gop/s W, or the clustered many-core architecture [7] which is based on 32 bit FP”
Survey of Machine Learning Accelerators (2020, methodology): “• Another Stanford chip, the TETRIS (cid:104) TETRIS (cid:105) [36], demonstrated highly efﬁcient inference by using 3-dimensional memory and a partitioning scheme that placed weights and data close to their processing elements.”
SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks (2018, methodology): “T ETRIS [8] and Neurocube [15] have almost the same compute engines as the previous CNN accelerators.”
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing (2019, unknown): “Many prior works explore near-memory processing using 3D/2.5D-stacked DRAM technology (e.g. HMC/HBM) [4], [8], [16], [20], [28]–[30], [39], [41], [43], [58].”
Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks (2020, background): “The need for higher speed and efficiency in DNN execution has led to an explosion of DNN accelerators [1, 3, 71–93] that has even made their way to operational datacenters (Google’s TPU [1], NVIDIA T4 [2], Microsoft Brainwave [3], etc.”
Efficient Processing of Deep Neural Networks: A Tutorial and Survey (2017, methodology): “Tetris [103] explores the use of HMC with the”
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture (2019, methodology): “Mapping DNN layers to a tile-based architecture is a well-studied research problem [15, 25, 50].”
Recent Advances in Convolutional Neural Network Acceleration (2018, background): “It saves more area for processing elements and leaves more space for accelerator design [130].”
Timeloop: A Systematic Approach to DNN Accelerator Evaluation (2019, background): “There is an abundance of excellent recent work on DNN accelerators [6], [13], [22], [26], [27], [32], [35]–[37].”
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach (2018, background): “It has been shown that the energy cost of moving data exceeds the cost of computation [11, 17], and so understanding and optimizing dataflow is a critical component of DNN accelerator design, as it directly determines how data is transferred between multipliers (L0), staged in local buffers (L1), an”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, methodology): “TETRIS [85], RENO [88], PRIME [86], ISAAC [87], Memristive Boltzmann Machine [89], PipeLayer [90], Atom-layer [91], ReCom [92], ReGAN [93], ReRAM ACC.”