Application of hardness-by-design methodology to radiation-tolerant ASIC technologies

By R. Lacoe, J. V. Osborn, R. Koga, S. Brown, D. C. Mayer. 2000

170 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/47d757f8d96825f284acf90854a313dd676ba64c

How researchers see this paper

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In Electrical and Electronic Engineering

1. M. Shaneyfelt
2. J. Schwank
3. Paul E. Dodd
4. J. Felix
5. R. Lacoe
6. D. Fleetwood
7. Lloyd W. Massengill
8. Pascale Gouker

Citations in the corpus

• Current and Future Challenges in Radiation Effects on CMOS Electronics (2010, methodology): “This technique has been proven to be very effective, enabling multi-Mrad(SiO ) TID hardness to be achieved in commercial technologies [40], [41].”
• Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology (2008, methodology): “When compared to standard-edged transistors, edgeless transistors have increased gate and source/drain capacitances [3], [28], [29].”