A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits

By Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang. 2005

361 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/5236066196cc07247c7e2d5f5062b30c3ac480ae

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Ashok Kumar
2. Sumeer Goel
3. Magdy A. Bayoumi
4. Mariano Aguirre-Hernandez
5. Mónico Linares Aranda

Citations in the corpus

• Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style (2006, methodology): “The proposed circuit uses only 2% more area when compared to the circuit in [7] but the circuit in [9] uses 43% more area.”