CNP: An FPGA-based processor for Convolutional Networks

By Clément Farabet, Cyril Poulet, Jefferson Y. Han, Yann LeCun. 2009

364 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

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Citations in the corpus

SqueezeNext: Hardware-Aware Neural Network Design (2018, methodology): “Weight Stationary WS is the most common method used in many notable neural network accelerators [5, 4, 7, 18, 2].”
Convolutional networks and applications in vision (2010, background): “group [51] achieves 10GOPS for 7x7 kernels, with an architecture that implements entire ConvNets, including pre/postprocessing, and is entirely programmable.”
Deep Learning on FPGAs: Past, Present, and Future (2016, background): “In this paper, Zhang et al. show their work to outperform most of the main strong competitors in this ﬁeld, including [14, 15, 23, 32, 33].”
Large-Scale FPGA-based Convolutional Networks (2011, methodology): “The pipelined implementation of this 2D convolver (as described in Farabet et al. (2009)), computes Equation 8 at every clock cycle. y1,i,j = x2,i,j + K−1∑ m=0 K−1∑ n=0 x1,i+m,j+nw1,m,n (8) In equation 8 x1,i,j is a value in the input plane, w1,m,n is a value in a K×K convolution kernel, x2,i,j is…”
Maximizing CNN accelerator efficiency through resource partitioning (2016, methodology): “For example, the 2D-convolvers used in [3, 10, 12, 22] must be provisioned for the largest filter across layers; they will necessarily be underutilized when computing layers with smaller filters.”
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network (2016, background): “To address this problem, many researchers have proposed various CNN acceleration techniques from either computing or memory access aspects [6, 7, 8, 9, 10, 11, 12, 13].”
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference (2016, methodology): “[7] describe a programmable ConvNet Processor (CNP), which is a RISC vector processor with specific macro-instructions for CNNs including 2D convolutions, 2D spatial pooling, dot product and an elementwise non-linear mapping function.”
Fused-layer CNN accelerators (2016, neutral): “In [6], [5], [16], systolic implementations were proposed.”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “CNP represents FMs and weights using 16-bit (Q8.”
Origami: A Convolutional Network Accelerator (2015, background): “2 Fixed-Point Analysis Previous work is not conclusive on the required precision for ConvNets, 16 and 18 bit are the most common values [14], [15], [17], [18].”
A high performance FPGA-based accelerator for large-scale convolutional neural networks (2016, background): “Hence, general purpose processors are not so efficient while a number of CNN implementations based on GPU [1], FPGA [7, 8, 9, 10, 11, 12, 13, 14, 15] even ASIC [16, 17, 18, 19] have been proposed.”
Hardware accelerated convolutional neural networks for synthetic vision systems (2010, methodology): “The FPGA was connected to external QDR-SRAM memory in a custom designed printed circuit board [8].”
NeuFlow: A runtime reconfigurable dataflow processor for vision (2011, methodology): “It can also perform on-the-ﬂy subsampling (spatial pooling), and simple dot-products (linear classiﬁers) [10] • the middle row PTs contain general purpose operators, such as squaring and dividing for divisive normalization, and other mathematical operators • the bottom row PTs implement non-linear…”