A high performance FPGA-based accelerator for large-scale convolutional neural networks

By Huimin Li, Xitian Fan, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang. International Conference on Field-Programmable Logic and Applications, 2016

322 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/5bb92336195e51ec1b22e5e67a0aaf2964df2513

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In Computer Vision and Pattern Recognition

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Citations in the corpus

FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, background): “On the other hand, they also noted that using one CLP for each stage of CONV layer in a fashion similar to that in [194] is not efficient due to three reasons.”
A survey of FPGA-based accelerators for convolutional neural networks (2018, unknown): “Batching converts an MVM operation into an MM operation, as shown in Fig.”
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks (2017, methodology): “Benefit from batch computing and using 2,144 DSP blocks, which enables high parallelism degree, [12] also achieves high throughput of 565.94 GOPS for AlexNet.”
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs (2018, background): “eresultsonVGG16, 2 AlexNet,andGoogLeNet.[32]implementsaternaryneuralnetwork on high-end Intel FPGAs and achieves higher performance/Watt than Titan X GPU. Most of the works mentioned above and others [33][34][35], target inefficient ConvNets on middle to high-end FPGA devices. For compact ConvNets, ”
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs (2020, methodology): “Most FPGA accelerators focus on the implementations of convolutional layers using the spatial algorithms [1], [2], [5]–[7], [12], [13], [45].”
Maximizing CNN accelerator efficiency through resource partitioning (2016, methodology): “Therefore, one way to construct a CNN accelerator with multiple CLPs is to implement a separate CLP for each layer [16].”
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection (2019, background): “The design in [14] also faces the same problem even though it delivers high performance for the AlexNet network.”
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA (2018, methodology): “Li et al. [28] used a pipeline design and accelerates all the layers concurrently on a single chip.”
Hu-Fu: Hardware and Software Collaborative Attack Framework Against Neural Networks (2018, background): “The ﬁrst one is input channel parallelism [34], [35].”
DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs (2018, background): “, [14] and [16]) have stored input feature maps on chip to achieve higher throughput and avoid complicated data movement.”
Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer (2017, methodology): “We also compare Escher to the batching strategy from [7] (Fudan) by setting Qy to dY/Pye, which corresponds to buffering the maximum amount of data per image.”