Large-Scale FPGA-based Convolutional Networks

By Clément Farabet, Yann LeCun, Koray Kavukcuoglu, Berin Martini, Polina Akselrod, Selçuk Talay, Eugenio Culurciello. 2011

134 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Media Technology, Model Architectures, ML Systems & Hardware

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Vision and Pattern Recognition

1. Luc Van Gool
2. Dacheng Tao
3. Xiaogang Wang
4. Trevor Darrell
5. Andrea Vedaldi
6. Chunhua Shen
7. Andrew Zisserman
8. Jitendra Malik

In Electrical and Electronic Engineering

1. Shih-Chii Liu
2. Daniel Neil
3. Ran El-Yaniv
4. G. Rose
5. Pascal Vincent
6. J. Douglas Birdwell
7. Andrew Zisserman
8. James S. Plank

In Media Technology

1. Cong Yao
2. Andrea Vedaldi
3. Andrew Zisserman
4. Xiang Bai
5. Victor S. Lempitsky
6. Yoshua Bengio
7. Max Jaderberg
8. Vadim Lebedev

In Model Architectures

1. Yoshua Bengio
2. Aaron C. Courville
3. Andrea Vedaldi
4. Pascal Vincent
5. Victor S. Lempitsky
6. Dacheng Tao
7. Cong Yao
8. Kyunghyun Cho

In ML Systems & Hardware

1. Aaron C. Courville
2. Matthieu Courbariaux
3. Ran El-Yaniv
4. Pascal Vincent
5. Andrea Vedaldi
6. Andrew Zisserman
7. Shih-Chii Liu
8. Yoshua Bengio

Citations in the corpus

• Speeding up Convolutional Neural Networks with Low Rank Expansions (2014, methodology): “[8] show that using bespoke FPGA implementations of CNNs can greatly increase processing speed.”
• Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations (2016, background): “…research efforts are invested in speeding up DNNs at run-time on both general-purpose (Vanhoucke et al., 2011; Gong et al., 2014; Romero et al., 2014; Han et al., 2015b) and specialized computer hardware (Farabet et al., 2011a,b; Pham et al., 2012; Chen et al., 2014a,b; Esser et al., 2015).”
• Representation Learning: A Review and New Perspectives (2012, methodology): “The main idea can be summarized by the following equation for the training criterion, which is simultaneously optimized with respect to hidden codes (representation) h(t) and with respect to parameters (W,α): JPSD = ∑ t λ‖h(t)‖1+‖x(t)−Wh(t)‖22+‖h(t)− fα(x(t))‖22 (26) where x(t) is the input vector f”
• Speeding-up Convolutional Neural Networks Using Fine-tuned CP-Decomposition (2014, background): “In many ways, this breakthrough has become possible through the acceptance of new computational tools, most notably GPUs (Krizhevsky et al., 2012), but also CPU clusters (Dean et al., 2012) and FPGAs (Farabet et al., 2011).”
• Binarized Neural Networks (2016, background): “…research efforts are invested in speeding up DNNs at run-time on both general-purpose (Vanhoucke et al., 2011; Gong et al., 2014; Romero et al., 2014; Han et al., 2015) and specialized computer hardware (Farabet et al., 2011a;b; Pham et al., 2012; Chen et al., 2014a;b; Esser et al., 2015).”
• DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients (2016, background): “…light of this, substantial research efforts are invested in speeding up DCNNs at both run-time and training-time, on both general-purpose (Vanhoucke et al., 2011; Gong et al., 2014; Han et al., 2015b) and specialized computer hardware (Farabet et al., 2011; Pham et al., 2012; Chen et al., 2014a;b).”
• Unsupervised Feature Learning and Deep Learning: A Review and New Perspectives (2012, methodology): “…feature learning approaches that were adapted to the convolutional setting include PSD (Kavukcuoglu et al. , 2009, 2010; Jarrett et al. , 2009; Farabet et al. , 2011; Henaff et al. , 2011), a convolutional version of sparse coding called deconvolutional networks (Zeiler et al. , 2010),…”
• Going Deeper with Embedded FPGA Platform for Convolutional Neural Network (2016, methodology): “Consequently, most of previous CNN accelerators used fixed-point numbers instead of floating-point numbers [7, 25, 26, 6].”
• Sparse Convolutional Neural Networks (2015, background): “[6] implement a large scale CNN based on FPGA infrastructure that can perform embedded real-time recognition tasks.”
• FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, unknown): “implementing architectures with large degree of parallelism resulting in high execution speeds [92].”
• Effective Quantization Methods for Recurrent Neural Networks (2016, methodology): “To alleviate these requirements, many methods have been proposed, from both hardware and software perspective (Farabet et al., 2011; Pham et al., 2012; Chen et al., 2014a;b).”
• BinaryNet: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1 (2016, background): “…devices, and much research work is done to speed-up DNNs at run-time on both general-purpose (Vanhoucke et al., 2011; Gong et al., 2014; Romero et al., 2014; Han et al., 2015) and specialized computer hardware (Farabet et al., 2011a;b; Pham et al., 2012; Chen et al., 2014a;b; Esser et al., 2015).”
• Big Data Deep Learning: Challenges and Perspectives (2014, methodology): “Other methods for large-scale deep learning also explore FPGA-based implementation [48] with a custom architecture: a control unit implemented in a CPU, a grid of multiple full-custom processing tiles, and a fast memory.”
• A Survey of Neuromorphic Computing and Neural Networks in Hardware (2017, background): “[867], [1068], the Google Street-View House Number (SVHN)”
• Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator (2014, background): “Computational vision typically presents a static image in a completed frame, but significant speedups can be achieved if visual information is processed in a frame-free manner [1], [2],”