Hardware accelerated convolutional neural networks for synthetic vision systems

By Clément Farabet, Berin Martini, Polina Akselrod, Selçuk Talay, Yann LeCun, Eugenio Culurciello. 2010

242 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

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Citations in the corpus

Deep Fried Convnets (2014, background): “Many other works have addressed the computational efficiency of convolutional networks in more specialized settings [13, 24].”
Large-Scale FPGA-based Convolutional Networks (2011, background): “Figure 2 shows a data-flow architecture whose goal is to process homogeneous streams of data in parallel (Farabet et al., 2010).”
A 240 G-ops/s Mobile Coprocessor for Deep Neural Networks (2014, methodology): “A similar FPGA implementation has been previously documented by Farabet in [6] and [7].”
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks (2016, unknown): “Keywords FPGA, OpenCL, Convolutional Neural Networks, Optimization.”
NeuFlow: A runtime reconfigurable dataflow processor for vision (2011, background): “Figure 1 shows a dataﬂow architecture that we designed to process homogeneous streams of data in parallel [9].”
Convolutional Neural Networks using Logarithmic Data Representation (2016, methodology): “For example (Farabet et al., 2010) developed Field-Programmable Gate Arrays (FPGA) to perform real-time forward propagation.”
Maximizing CNN accelerator efficiency through resource partitioning (2016, methodology): “For example, the 2D-convolvers used in [3, 10, 12, 22] must be provisioned for the largest filter across layers; they will necessarily be underutilized when computing layers with smaller filters.”
From high-level deep neural models to FPGAs (2016, background): “[15, 28] develops an FPGA accelerator for a specific DNN.”
Adaptive Convolutional Neural Network and Its Application in Face Recognition (2015, unknown): “To solve this problem, some studies are on hardware acceleration, which is made to speed up the performance comparison, for instance, GPU-based programming and scalable hardware architecture [5–7].”
Traffic sign recognition with multi-scale Convolutional Networks (2011, background): “Embedded systems based on FPGAs can run large ConvNets in real time [11], opening the possibility of performing multiple vision tasks simultaneously with a common infrastructure.”
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators (2016, unknown): “References: CPUs [8] [9] [10] [11] [12], GPUs [13] [14] [15] [16] [8] [9] [11], FPGAs [17] [12], and ASICs [18] [19] [20] [21] [13] [22] [12] [23]. outputs from new input data.”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “in [127] and [142] was presented in [143] and referred to as neuFlow.”