FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

By Ahmad Shawahna, Sadiq M. Sait, Aiman H. El-Maleh. IEEE Access, 2019

445 citations recorded by the source corpus.

Due to recent advances in digital technologies, and availability of credible data, an area of artificial intelligence, deep learning, has emerged and has demonstrated its ability and effectiveness in solving complex learning problems not possible before. In particular, convolutional neural networks (CNNs) have demonstrated their effectiveness in the image detection and recognition applications. However, they require intensive CPU operations and memory bandwidth that make general CPUs fail to achieve the desired performance levels. Consequently, hardware accelerators that use application-specific integrated circuits, field-programmable gate arrays (FPGAs), and graphic processing units have been employed to improve the throughput of CNNs. More precisely, FPGAs have been recently adopted for accelerating the implementation of deep learning networks due to their ability to maximize parallelism and their energy efficiency. In this paper, we review the recent existing techniques for accelerating deep learning networks on FPGAs. We highlight the key features employed by the various techniques for improving the acceleration performance. In addition, we provide recommendations for enhancing the utilization of FPGAs for CNNs acceleration. The techniques investigated in this paper represent the recent trends in the FPGA-based accelerators of deep learning networks. Thus, this paper is expected to direct the future advances on efficient hardware accelerators and to be useful for deep learning researchers.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/cc557a8b361445db05d5b7211fec4ad5aa7f97b3

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Vision and Pattern Recognition

1. Bashir I. Morshed
2. Syed Kamrul Islam
3. Jianlin Cheng
4. Md Maruf Hossain Shuvo

In Electrical and Electronic Engineering

1. Bashir I. Morshed
2. Syed Kamrul Islam
3. Jianlin Cheng
4. Md Maruf Hossain Shuvo

Citations in the corpus

• Application of the residue number system to reduce hardware costs of the convolutional neural network implementation (2020, methodology): “The recent existing methods of acceleration the deep learning network on FPGA are discussed in [29].”
• Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review (2023, methodology): “Due to the increased demand for EI, small and high-density FPGAs are now being considered [11], [315], [316], [317].”