Going Deeper with Embedded FPGA Platform for Convolutional Neural Network

By Jiantao Qiu, Jie Wang, Song Yao, Kaiyuan Guo, Boxun Li, Erjin Zhou, Jincheng Yu, Tianqi Tang, Ningyi Xu, Sen Song and 2 more. Symposium on Field Programmable Gate Arrays, 2016

1,200 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/c382406fd8db2744b2a609837395e5da05e1d2ed

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In Computer Vision and Pattern Recognition

In Electrical and Electronic Engineering

Citations in the corpus

Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer (2017, methodology): “[13] uses data quantization to reduce the word size for both convolutional layers and fully-connected layers, and further uses SVD decomposition to compress the weights in fully-connected layers.”
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA (2016, result): “Other similar works also present FPGA-based neural network accelerators [9].”
A^3: Accelerating Attention Mechanisms in Neural Networks with Approximation (2020, background): “CNN accelerators for custom ASIC or FPGA device [1], [2], [3], [61], [62], [63], [64], [65], [66], [67] and RNN accelerators [3], [68], [69], [70] are proposed to accelerate NN processing by exploiting massive parallelism and optimizing data movements.”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “The experimental results show that the proposed accelerator has a throughput of 645.25 GOPS, which is more than 3 .”
Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? (2017, background): “There has been a plethora of prior work focusing on FPGA-based deep learning accelerators (e.g., [10,11]).”
CSRNet: Dilated Convolutional Neural Networks for Understanding the Highly Congested Scenes (2018, background): “The additional bonus of using DNNs comes from the enthusiastic hardware community where DNNs are rapidly investigated and implemented on GPUs [13], FPGAs [14, 15, 16], and ASICs [17].”
Hello Edge: Keyword Spotting on Microcontrollers (2017, methodology): “In this work, we use the quantization flow described in [34] using 8-bits to represent all the weights and activations.”
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating (2019, methodology): “Similar to several other CNN accelerators [16–18], we add a specialized line buffer between the window buffers and the global feature buffer to further exploit the data locality and reuse of the feature maps.”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, background): “Due to their insatiable demand for compute power, naturally, both the research community [1–28] as well the industry [29–31] have turned to accelerators to accommodate modern DNN computation.”
EIE: Efficient Inference Engine on Compressed Deep Neural Network (2016, methodology): “However, it has been found that fully-connected (FC) layers, widely used in RNN and LSTMs, are bandwidth limited on large networks [14].”
FPGA/DNN Co-Design: An Efficient Design Methodology for 1oT Intelligence on the Edge (2019, methodology): “On the other hand, for FPGA-based DNN accelerator, recent technologies such as quantization [2, 4] and model compression [15] are used to reduce DNN model size, and latency-directed resource allocation [3] and fine-grained pipeline architecture [5] are proposed to deliver low latency during DNN”
Hardware-oriented Approximation of Convolutional Neural Networks (2016, methodology): “In Figure 1, m and n refer to the number of bits for layer outputs and layer weights, respectively.”
Hu-Fu: Hardware and Software Collaborative Attack Framework Against Neural Networks (2018, methodology): “The second one is pixel parallelism which means a single width × height kernel is computed in parallel and added up in the same add-tree or MAC [8], [36].”
The History Began from AlexNet: A Comprehensive Survey on Deep Learning Approaches (2018, background): “observed that each case delayed down-sampling led to higher classification accuracy [265].”
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs (2018, methodology): “[39, 41, 42] have achieved high frame rate on smaller devices, however, the accuracy of their network is not on par with [40] for ImageNet classification.”
Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks (2016, methodology): “As a result, Caffeine can achieve high performance for both the computation-bound CONV layer (96 GFLOPS and 365 GOPS, implementing a VGG16 network on a single KU060 FPGA board) and communication-bound FCN layer (45 GFLOPS and 173 GOPS, more than 100x speedup over prior work [23]).”