NeuFlow: A runtime reconfigurable dataflow processor for vision

By Clément Farabet, Berin Martini, Benoit Corda, Polina Akselrod, Eugenio Culurciello, Yann LeCun. 2011

391 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, ML Systems & Hardware

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Citations in the corpus

Deep Learning with Limited Numerical Precision (2015, methodology): “We also employ to denote the smallest positive number that may be represented in the given ﬁxed-point format.”
Binarized Neural Networks (2016, background): “…research efforts are invested in speeding up DNNs at run-time on both general-purpose (Vanhoucke et al., 2011; Gong et al., 2014; Romero et al., 2014; Han et al., 2015) and specialized computer hardware (Farabet et al., 2011a;b; Pham et al., 2012; Chen et al., 2014a;b; Esser et al., 2015).”
SqueezeNext: Hardware-Aware Neural Network Design (2018, methodology): “Weight Stationary WS is the most common method used in many notable neural network accelerators [5, 4, 7, 18, 2].”
A 240 G-ops/s Mobile Coprocessor for Deep Neural Networks (2014, methodology): “A similar FPGA implementation has been previously documented by Farabet in [6] and [7].”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, background): “Due to the high demand of computing power in DL applications, we have recently witnessed a phenomenal trend in which the landscape of computing has shifted from general-purpose processors to domain-specific architectures [16–110].”
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (2017, methodology): “Neuflow [15], ShiDianNao [12], and Eyeriss [8] utilized 2D spatial PE arrays with specialized interconnects to match the 2D convolution pattern.”
Project Adam: Building an Efficient and Scalable Deep Learning Training System (2014, background): “The vision and computer architecture community has started to explore hardware acceleration for neural network models for vision [3, 4, 10, 16, 22].”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, background): “in [127] and [142] was presented in [143] and referred to as neuFlow.”
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory (2016, background): “As a result, early on-chip cache solutions [4], [8] were tried but they were not scalable to large neural networks or complex applications over large data sets, e.g., high resolution image and extracted features [4].”
HarDNet: A Low Memory Traffic Network (2019, background): “Some researchers pointed out that limited memory bandwidth can dominate the inference latency and power consumption in GPU-based systems [25,27], FPGA-based systems [5,13], or custom accelerators [6,7,11].”
NeuFlow: Dataflow vision processing system-on-a-chip (2012, background): “Figure 1 reports the neuFlow architecture [6], which is designed to accelerate data stream ConvNets computation.”
BinaryNet: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1 (2016, background): “…devices, and much research work is done to speed-up DNNs at run-time on both general-purpose (Vanhoucke et al., 2011; Gong et al., 2014; Romero et al., 2014; Han et al., 2015) and specialized computer hardware (Farabet et al., 2011a;b; Pham et al., 2012; Chen et al., 2014a;b; Esser et al., 2015).”
Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform (2014, methodology): “For example, Farabet et al. [11] introduce NeuFlow, a FPGAbased dataflow processor designed explicitly to maximize performance with convolutional neural network algorithms.”
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA (2018, background): “CVPR 2011 [29] Xilinx Virtex6 240t N/A yes yes N/A N/A no”
Energy-efficient ConvNets through approximate computing (2016, background): “A number of ConvNet hardware optimizations [2] [15], coprocessors [6] and accelerators such as DianNao [1] have been proposed.”
DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning (2014, methodology): “Interestingly, machine-learning researchers who have recently dipped into hardware accelerators [13] have made the same choice.”