Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

By Kaushik Roy, Saibal Mukhopadhyay, H. Mahmoodi-Meimand. Proceedings of the IEEE, 2003

2,523 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/0170445683d4197e05032c2769faf829c3f017fd

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In Electrical and Electronic Engineering

Citations in the corpus

Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies (2006, background): “The drain-induced-barrier lowering (DIBL) effect is included in all the operation regions of the transistor and represents the dependency of on [11].”
Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits (2015, background): “One of the transistors (designated as block) is in a state of negative gate-to-source bias (this is due to the so-called stacking effect [42]) and thus has an even higher resistance OFF state that effectively blocks any leakage current.”
The role of contact resistance in graphene field-effect devices (2017, background): “Few atomic layers are almost at the physical limit of the scaling process and quantum mechanical phenomena become relevant to the device performance, causing increase of the gate leakage current due to electron tunneling already at low bias and field emission at higher bias [30].”
CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques (2011, background): “Equation 3 [12] shows the gate leakage current density.”
An integrated GPU power and performance model (2010, background): “Even though the evaluated GPU does not employ power gating, idle SMs do not consume as much power as active SMs do because of low-activity factors [18] (i.”
Retrospective: Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors (2023, neutral): “This is due to various leakage mechanisms by which charge can disperse: e.g., subthreshold leakage [56] and gate-induced drain leakage [57].”
Effect of Drain Doping Profile on Double-Gate Tunnel Field-Effect Transistor and its Influence on Device RF Performance (2014, background): “of incremental short channel effects and leakage currents [10], [11], making it unsuitable for analog/RF applications.”
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors (2014, background): “, subthreshold leakage [56] and gate-induced drain leakage [57].”