Brian Rogers
International Symposium on Computer Architecture · 2006–2009
A researcher in the Science corpus: 2 papers; trusts 1 researcher and is trusted by 0 researchers here, as inferred from the citation graph.
Whom Brian Rogers trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
Papers from Brian Rogers's perspective
Ordered by how strongly the researchers Brian Rogers trusts endorse each paper. Same corpus, a different order for every researcher.
- The PARSEC benchmark suite: Characterization and architectural implications (International Conference on Parallel Architectures and Compilation Techniques)
- Die Stacking (3D) Microarchitecture (Micro)
- Heterogeneous chip multiprocessors (Computer)
- The Galois/Counter Mode of Operation (GCM)
- Caches and hash trees for efficient memory integrity verification (The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.)
- Architectural support for copy and tamper resistant software
- Single-ISA heterogeneous multi-core architectures for multithreaded workload performance (Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.)
- Amdahl's Law in the Multicore Era (Computer)
- Adaptive cache compression for high-performance processors (Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.)
- SP 800-38C. Recommendation for Block Cipher Modes of Operation: the CCM Mode for Authentication and Confidentiality
Their papers
- Scaling the bandwidth wall: challenges in and avenues for CMP scaling (2009) — 310 citations
- Improving Cost, Performance, and Security of Memory Encryption and Authentication (2006) — 295 citations