A dynamic voltage scaled microprocessor system

By T. Burd, Trevor Pering, A. Stratakos, Robert W. Brodersen. IEEE Journal of Solid-State Circuits, 2000

1,014 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/b3a6c4da726ad94308029e86bbb3cdb88cdec9cb

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Biomedical Engineering

1. Dimitrios D. Vergados
2. Nikolaos A. Pantazis

In Electrical and Electronic Engineering

1. David T. Blaauw
2. Sanjay Pant
3. Shidhartha Das
4. Saibal Mukhopadhyay
5. Dimitrios D. Vergados
6. Kaushik Roy
7. Nikolaos A. Pantazis
8. Yonghong Tian

In Hardware and Architecture

1. David T. Blaauw
2. Saibal Mukhopadhyay
3. Dimitrios D. Vergados
4. Kaushik Roy
5. Nikolaos A. Pantazis

Citations in the corpus

• Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits (2003, background): “When performance demand is low, supply voltage and clock frequency is lowered, delivering reduced performance but with substantial power reduction [76].”
• Scheduling with dynamic voltage/speed adjustment using slack reclamation in multi-processor real-time systems (2001, neutral): “For the lpARM processor that needs 70 s to change voltage [5], C = 0:7% andK = 0.”
• Power and temperature control on a 90-nm Itanium family processor (2006, background): “While other systems have minimized power by modulating VF [2], [3], they”
• Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads (2002, background): “VNW (1) where VthO is the zero-bias threshold voltage, If>s' y, and eD/BL are constants for a given technology, Vbs is the voltage applied between the body and source of the transistor, 6.”
• Dynamic thermal management for high-performance microprocessors (2001, neutral): “Obviously this requires detailed timing analysis and careful attention to circuit design choices [6].”
• A Multistage Interleaved Synchronous Buck Converter With Integrated Output Filter in 0.18 $\mu$m SiGe Process (2007, background): “High efficiency, high bandwidth SM dc–dc converters are the best candidates for supplying the RF PA [6], [7], memory chips, and digital base-band cores [8].”
• A survey on power control issues in wireless sensor networks (2007, methodology): “IEEE Communications Surveys & Tutorials • 4th Quarter 2007 91 • The intra-task timeslot VS technique [ 17 , 18] • The proposed buffering VS technique [16, 17] • The proposed technique with multiple subtasks (for both of best and average execution time assumptions) [16‐18] show that the proposed tech”
• Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance (2008, methodology): “Traditional methods for adaptive design have used so-called canary circuits that mimic the critical-path delay of the actual design [1-4].”
• A self-tuning DVS processor using delay-error detection and correction (2005, neutral): “Traditional techniques [2]–[6] described in literature use”