Power and temperature control on a 90-nm Itanium family processor

By R. McGowen, Christopher Poirier, C. Bostak, J. Ignowski, M. Millican, Warren H. Parks, S. Naffziger. IEEE Journal of Solid-State Circuits, 2006

306 citations recorded by the source corpus.

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An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget (2006, methodology): “For per-core power information, we assume the presence of on-core current sensors, similar to those available in the Foxton controller of the Montecito chip [30, 36].”
Server-Level Power Control (2007, background): “Foxton [ 19 ], which is not yet available in products, uses on-chip power measurement to control power in a single Itanium processor.”
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008, methodology): “To run a power management algorithm such as LinOpt, we need on-chip sensors that provide power consumption information as in Itanium II [22], on a per-core basis.”
Thread motion: fine-grained power management for multi-core systems (2009, methodology): “The last level cache (L2) resides on a separate VF domain and accesses to it complete in fixed time [21].”