Parameter variations and impact on circuits and microarchitecture

By Shekhar Y. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De. Proceedings - Design Automation Conference, 2003

1,529 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/a71e5f98a7576a35ac2fb3a9843c3d9d8e7d745c

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In Electrical and Electronic Engineering

Citations in the corpus

Thousand Core ChipsA Technology Perspective (2007, background): “Resiliency As technology scales further, variations become prominent [5].”
McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures (2009, neutral): “Chip-to-chip power variation in recent microprocessor designs [7] is also comparable to the magnitude of the power validation errors reported in Table 1.”
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008, background): “Indeed, variation has major implications, such as increased leakage power consumption in the chips and limited processor frequency improvements [2].”
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS (2005, methodology): “HE random variations in process parameters have emerged as a major design challenge in circuit design in the nanometer regime [1]–[ 3 ].”
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits (2010, background): “Fig. 5 shows that performance variation due to global process variation alone increases by approximately 5X from � 30% (1.3X) [ 22 ] at nominal operating voltage to as much as 400%, (5X) at 400 mV. Operating at this voltage also heightens sensitivity to temperature and supply ripple, each of which c”
Designing reliable systems from unreliable components: the challenges of transistor variability and degradation (2005, background): “Impact of variations Static and dynamic variations have impact even on today’s VLSI chips, and it’s expected to get worse as technology scales.(3) Today, we see the effect predominantly as a 30 percent variation in operating frequency and 5 to 10”
Process Variation Tolerant 3T1D-Based Cache Architectures (2007, background): “Researchers have shown that the selection of pipeline depth [ 4 , 15] and other microarchitectural parameters, at design time, can significantly impact the susceptibility of an architecture to process variations.”
VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects (2008, background): “…and Resulting Timing Errors for Microarchitects Smruti R. Sarangi, Brian Greskamp, Student Member, IEEE, Radu Teodorescu, Student Member, IEEE, Jun Nakano, Member, IEEE, Abhishek Tiwari, Student Member, IEEE, and Josep Torrellas, Fellow, IEEE Abstract—Within-die parameter variation poses a major…”