Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

By Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005

512 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/7587501db85e6b05840a89140748d517d3007c1e

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Josep Torrellas
2. Radu Teodorescu
3. Keejong Kim
4. Kaushik Roy
5. Smruti Ranjan Sarangi
6. Jaydeep P. Kulkarni
7. Yonghong Tian

In Hardware and Architecture

1. Josep Torrellas
2. Radu Teodorescu
3. Kaushik Roy

Citations in the corpus

• ERSA: Error Resilient System Architecture for probabilistic applications (2010, unknown): “[Mukhopadhyay 05] S. Mukhopadhyay, Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS , IEEE Trans.”
• A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM (2007, background): “, read failure, hold failure, access time failure, and write failure [4].”
• VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects (2008, methodology): “1) Using Shockley Model: The model in [26] uses the traditional Shockley long channel transistor equations.”
• Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008, background): “[23] for the access time of a 6-transistor SRAM cell, to include the time to access the whole SRAM structure.”