VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

By Smruti Ranjan Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, A. Tiwari, Josep Torrellas. IEEE transactions on semiconductor manufacturing, 2008

433 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/37204b89f7a1276fa572ed5bf6dab49185cc2d61

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Josep Torrellas
2. Radu Teodorescu

In Hardware and Architecture

1. Josep Torrellas
2. Radu Teodorescu

Citations in the corpus

• Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008, methodology): “To model WID variation, we use the VARIUS model [30, 37] to generate Vth and Leff variation maps.”